1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to an internal clock generation circuit suitable for use in a synchronous semiconductor memory device activated in synchronism with a system clock.
2. Description of the Related Art
A semiconductor memory device operated in synchronism with a system clock supplied thereto has recently been required to speed up its operating speed with an increase in the frequency of the system clock. Therefore, a transfer delay time between the input of the system clock to the semiconductor memory device and the output of data therefrom becomes large relative to a clock cycle of the system clock. Thus, this leads to a malfunction.
FIG. 13(a) shows a data output-timing chart of a semiconductor memory device activated in synchronism with a system clock. The drawing shows the manner in which the system clock (hereinafter called xe2x80x9cexternal clock "PHgr"exfxe2x80x9d) inputted to the semiconductor memory device is transferred within the semiconductor memory device with a delay time td0 and defined as a data output timing clock CLKd, and date "PHgr"out is outputted in synchronism with the clock. The data "PHgr"out is outputted with a delay dout of an output circuit with respect to the clock CLKd. The data is transmitted and received according to a strobe signal "PHgr"s.
When, however, the operating frequency of the external clock xcfx86ext becomes high, the strobe signal xcfx86s is outputted before the output of xcfx86out is fixed, so that a malfunction occurs.
In order to solve such a problem, an internal clock generation circuit such as Phase Locked Loop (PLL), Delay Locked Loop (DLL) employed in a semiconductor memory device has been proposed to implement chip""s internal operations synchronized with a system clock.
FIG. 14 is a schematic diagram of a conventional internal clock generation circuit. The internal clock generation circuit comprises a delay line 102 for generating such amount of a delay thereof as to minimize the phase difference between an external clock "PHgr"ext and a data output "PHgr"out, a control circuit 200 for controlling the delay line 102, and a monitor circuit 106 for monitoring a delay amount of an output circuit 104 of a semiconductor memory device.
The control circuit 200 comprises a phase comparator 100 and a shift register 101. The phase comparator 100 compares the phase of the external clock xcfx86ext and that of a clock xcfx86fd, which is obtained by delaying an internal clock xcfx86int by a delay time dout of the output circuit 104 via the monitor circuit 106 and fed back from the monitor circuit 106 to thereby detect the phase difference therebetween and outputs a detected signal xcfx861 to the shift register 101. The shift register 101 counts the detected signal xcfx861 and outputs a control signal xcfx862 to the delay line 102 in response to the detected signal xcfx861 to control the delay line 102.
The delay line 102 is controlled according to the control signal xcfx862 and controls or adjusts such a delay amount as to minimize the phase difference between the external clock xcfx86ext and the data output xcfx86out.
FIG. 16 is a data output timing chart of the circuit shown in FIG. 14. When the external clock xcfx86ext is inputted to the delay line 102, the amount of a delay of the delay line 102 is controlled by the control signal xcfx862 so that such an internal clock xcfx86int that the delay amount tLine becomes tLine=tCKxe2x88x92dout (where tCK: cycle time of clock), is generated. It is therefore feasible to provide a data output xcfx86out minimized in delay with respect to the external clock xcfx86ext. Thus, the internal clock generation circuit generates such an internal clock xcfx86int as to achieve data output xcfx86out delayed by one cycle from the external clock xcfx86ext.
FIG. 15 is a diagram showing a circuit configuration of the delay line 102 lying within the conventional internal clock generation circuit. As shown in FIG. 15, the delay line 102 comprises delay elements 202 and selects any of TAPs (TAP1 through TAPn) thereof in response to a control signal xcfx862 to control the number of effective delay elements, thereby controlling or adjusting the amount of a delay of the external clock xcfx86ext. Incidentally, a unit delay time of each delay element 202 will be defined as a delay step.
However, the conventional internal clock generation circuit is accompanied by a problem in that since an internal clock generable frequency range is determined based on (delay step)xc3x97(number of delay elements), the number of the delay elements must be increased to generate the internal clock in a wide frequency range when the delay step is reduced, thus leading to an increase in chip area. When the operating frequency is 66 MHz, for example, the cycle time of a clock results in 15 ns. The number of the delay elements at the time that the delay step is 0.30 ns, needs 15÷0.30=50. Assuming that the delay step is set to 0.15 ns equivalent to one-half the delay step of 0.30 ns at this time, the number of the delay elements needs 100 equivalent to twice the number of the delay elements 50.
An object of the present invention is to provide an internal clock generation circuit capable of controlling an increase in chip area while reducing a delay step of a delay line and generating an internal clock in a wider frequency range.
In order to achieve the above object, there is provided an internal clock generation circuit according to the present invention, comprising a phase comparator, a shift register, a filter, a monitor circuit, and a plurality of delay lines such as first and second delay lines. The first delay line has delay steps each larger than that of the second delay line. The first delay line is first used to generate a clock minimized in phase difference with respect to an external clock. The clock signal is inputted to the second delay line to perform fine adjustment to the phase difference.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.